Frequency equalization is often required in high speed telecommunication links to compensate for the high frequency attenuation and nonlinear group delay characteristics of lossy channels. These deleterious effects are due to the distributed capacitance, resistance and inductance found in lossy channels (e.g., coaxial cable, twisted pair wiring, and circuit board traces) that are used to connect transmitters and receivers across long distances in high speed telecommunication links.
When high speed communication signals are passed through a lossy channel, they exhibit time domain distortion and loss of symmetry due to the high frequency attenuation and nonlinear group delay characteristics. The loss of symmetry causes the placement of zero crossings to be dependent on the history of previous symbols sent through the channel. In this way, the resulting placement in time of the zero crossings is variable and appears to be “jitter.” This jitter is defined as data dependent “deterministic jitter” (designated with the letters “DJ”).
It is desirable to provide the users of high speed telecommunication links with a frequency equalizer that senses the loss in the channel and automatically adapts to provide a boost that compensates for this loss within the frequency band of interest. From a frequency domain standpoint, the equalizer should have the inverse Fourier transform of the lossy channel for frequencies up to half the data rate to satisfy the Nyquist criteria. When the equalization procedure is done correctly, the deterministic jitter (DJ) is minimized in the data path. Minimizing deterministic jitter (DJ) is desirable in order to reduce errors in the subsequent clock and data recovery subsystem of the receiver.
It is also desirable that the servo mechanism of the adaptive equalizer not require sampling clocks in order to operate. This is because the sampling clocks would need to be generated by a clock recovery system in order to be coherent with the received data. The clock recovery system would require its own feedback loop and the interaction of the clock recovery feedback loop with the equalizer adaptation loop has the potential to cause instabilities that would make the system difficult to apply in a wide range of customer applications.
It is also desirable that the adaptive equalizer servo loop works well with multiple data rates in order to simplify customer usage in systems that require backward compatibility with older standards (and therefore lower data rates).
In addition, the adaptive equalizer should not add excessive amounts of thermal noise to the data path. Thermal noise adds random jitter (designated with the letters “RJ”) to the data path output.
The “total jitter” within the data path is the sum of the deterministic jitter (DJ) that is due to the lossy channel and the random jitter (RJ) that is due to the thermal noise of the adaptive equalizer. It is desirable that an adaptive equalizer have an unconditionally stable servo loop that minimizes the “total jitter” present in the data path.
Thermal noise generally increases as the equalizer boost is increased. At the same time, as the channel loss is increased, it follows that it will be necessary for the servo loop to increase the adaptive equalizer boost in order to reduce the deterministic jitter (DJ). In practice, there is an upper limit to the amount of boost than an equalizer can add. This upper limit is set by the amount of random jitter (RJ) that is added to the overall system by the equalizer data path as a function of the boost required to compensate high frequency attenuation of the lossy channel.
Implementations of practical high speed integrated circuit boost stages use RC time constants to create increased high frequency gain. As a result, a practical transistor implementation of the equalizer can only provide a six decibel (6 dB) per octave boost per stage. Lossy channels exhibit a transfer characteristic that may be described as follows:H(j2πf)=e−jkL√{square root over (f)}  (1)
The constant “k” in Equation (1) is a constant that is determined empirically. The letter “L” represents the cable length. It can be shown from Equation (1) that the slope of the transfer characteristic is a function of the cable length L. It follows that the equalization of very lossy cables requires a multi-stage topology of the type shown in FIG. 1.
FIG. 1 illustrates a prior art multi-stage adaptive equalizer circuit 100 comprising N stages (110, 120, 130) and a slicer circuit (140). Input is provided to the first adaptive equalizer stage 110 (Stage 1). The output of stage 110 (Stage 1) is provided to the second adaptive equalizer stage 120 (Stage 2). The output of stage 120 (Stage 2) is provided to the next adaptive equalizer stage (not shown). The output of the next to the last adaptive equalizer stage (not shown) is provided to the last adaptive equalizer stage 130 (Stage N). The output of stage 130 (Stage N) is provided to the slicer circuit (140).
Each of the adaptive equalizer stages (110, 120, 130) shown in FIG. 1 comprises a circuit of the type shown in FIG. 2. FIG. 2 illustrates a prior art adaptive equalizer stage 200 that comprises a gain unit 210, an adder circuit 220, a high pass filter circuit 230 and a tunable high frequency gain unit 240. The direct current (DC) path comprises the gain unit 210 and the adder circuit 220. The high pass filter circuit 230 and the tunable high frequency gain unit 240 are coupled in parallel with the direct current (DC) path.
The boost that is provided by adaptive equalizer circuit 200 is adjusted by the tunable high frequency gain unit 240. The variable gain is designated by the symbol “αi” (“alpha sub i”). The variable gain can range from zero (“0”) for “no boost” to one (“1”) for “maximum boost.” The resulting transfer function of the adaptive equalizer stage can realize an approximation of the inverse Fourier transform of the lossy channel.
The accuracy of this approximation will be limited by the bandwidth limit of the circuit and also by the fact that in practical implementations, the high pass filter circuit 230 will only have a six decibel (6 dB) per octave slope due to the nature of a single RC time constant. If the slope of the attenuation of the lossy channel is greater than six decibels (6 dB) per octave, then several equalizer boost stages be cascaded in series to better approximate the inverse Fourier transfer characteristic of the lossy channel. The improved approximation of the inverse Fourier transfer characteristic will result in lower deterministic jitter (DJ) output.
The next challenge to be solved in the design of an efficient adaptive equalizer circuit is to create a servo loop that controls the variable gain “α” of each of the individual stages so that the lossy channel deterministic jitter (DJ) is minimized. In a multi-stage adaptive equalizer system the cascaded adaptive equalizer stages are driven in a thermometer fashion in which only the first stage (i.e., Stage 1) provides a high frequency boost to compensate for moderately lossy channels (implying less loss) and in which the variable gain “α” for the remaining stages is held at zero (“0”) so that the remaining stages realize flat gain characteristics.
Then the next stage (i.e., Stage 2) is boosted when additional equalization for lossier channels is required. The remaining adaptive equalizer stages are brought on line as required. Finally, all of the adaptive equalizer stages are used to provide a boost for the lossiest channels.
In order to better understand the operation of the servo feedback system that controls the variable gain “α” coefficients of the adaptive equalizer boost stages, the data path will now be described in more detail. FIG. 3 illustrates a block diagram of a prior art transmitter 310, a lossy channel 320, the adaptive equalizer stages (110, 120, 130), and slicer circuit 140. FIG. 3 also indicates the corresponding frequency domain responses of the various blocks.
The slicer circuit 140 is a limiting amplifier. The slicer circuit 140 constitutes the first nonlinear element in the data path. Assuming that the adaptive equalizer stages are correctly tuned, the frequency content within the frequency equalization range at the input and at the output of the circuit shown in FIG. 3 is identical (except for a scaling factor that is equal to Gs/[(Gc)(Gtx)]. The term Gs represents the amplitude of the slicer output. The term Gc represents the DC gain of the channel. The term Gtx represents the amplitude of the cable driver output.
In the manner described above a channel equalizer may be constructed from a cascade of adaptive equalizer stages in which each of the adaptive equalizer stages has a nominal slope of six decibels (6 dB) per octave. It is desirable for the channel equalizer to have a servo loop that automatically adapts the variable gain “α” coefficients of the adaptive equalizer stages.
It may be seen from FIG. 3 that one way to adapt the variable gain “α” coefficients is to compare the energy of the signal at the output of the last adaptive equalizer stage 130 (Stage N) to the energy of the “squared up” signal at the output of the slicer 140. This approach would work well if the lossy channel 320 had only a high frequency response loss. In actuality the lossy channel 320 also has a low frequency “direct current” (DC) loss due to finite resistance. It is therefore necessary to compensate for the DC attenuation loss as well.
That is, the feedback signal that is used to control the servo adaptation mechanism cannot be based solely on a comparison between the input and output signals of the slicer 140. Some additional mechanism must be included that compensates for the DC attenuation loss of the lossy channel 320.
One prior art approach to the problem uses a variable gain amplifier (VGA) instead of a unity gain amplifier in each of the adaptive equalizer stages. This approach is described in a paper by J. Choi, M. Hwang and D. Jeong entitled “A 0.18 μm CMOS 3.5 Gb/s Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Control Method” in IEEE J. Solid-State Circuits, Volume 39, pp. 419-425 (March 2004).
FIG. 4 illustrates a prior art adaptive equalizer circuit 400 of the type employed in the method of J. Choi et al. Adaptive equalizer circuit 400 comprises a variable gain amplifier (VGA) 410, an adder circuit 420, a high pass filter circuit 430 and a tunable high frequency gain unit 440. The direct current (DC) path comprises the variable gain amplifier (VGA) 410 and the adder circuit 420. The high pass filter circuit 430 and the tunable high frequency gain unit 440 are coupled in parallel with the direct current (DC) path.
The variable gain amplifier (VGA) is controlled by a separate feedback loop (not shown) that adjusts directly in response to the low frequency content of the signal. Therefore, the final topology employed in the method of J. Choi et al. requires two nested control loops. One of the control loops is for the low frequency variable gain amplifier (VGA) gain. The other control loop is for the adaptation of the adaptive equalizer stages.
It is very difficult to guarantee the simultaneous convergence of two nested control loops under all conditions for customer applications. If there is a non-monotonic convergence space, both control loops can interfere with each other. This can result in multiple non-optimal locking points.
A second prior art approach is described in a paper by M. H. Shabika entitled “A 2.5 Gb/s Adaptive Cable Equalizer” in IEEE Int. Solid-State Circuits Conference Dig. Tech. Papers, pp. 396-397, February 1999. Instead of using a separate control loop, the variable gain amplifier (VGA) can be driven from the same adaptive equalizer main loop. But the approach suggested by Shabika still does not overcome the intrinsic limitation of having a DC gain in the equalizer.
To better understand the limitation, note that adding a DC path gain greater than unity in parallel with the high pass filter (HPF) boosting stage reduces the effective amount of boost. Consider a cable having a three decibel (3 dB) attenuation point at a frequency Fcutoff. Its equalizer counterpart is required to compensate for the high frequency attenuation. With a unity gain DC path, the equalizer needs a gain of three decibels (3 dB) at this frequency. If on the other hand, a variable gain amplifier (VGA) is used in the DC path, the equalizer will have a DC gain of 1/G0 where G0 is the DC loss of the cable.
As a consequence, the equalizer gain is now shifted up to 3 dB+20 log (1/G0) at the frequency Fcutoff. For an optimum design, this additional requirement will translate into higher power drawn in the equalizer stage.
Therefore, there is a need in the art for a system and method that is capable of providing an improved adaptive equalizer circuit that overcomes the above identified deficiencies of the prior art.